1. Field of the Invention
This invention pertains generally to integrated circuits, and more particularly to transistor source configurations and control methods for suppressing leakage current.
2. Description of Related Art
Leakage current is a critical parameter to be controlled and managed in fabricating ultra-deep sub-micron VLSI design. For example, in regard to 0.09 μm technology, leakage current is expected to comprise about 30˜40% of total chip power consumption. One issue that arises for leakage suppression techniques in source transistors is fast recovery of the virtual power line level, when the chip is changed into active mode from standby mode, so as not to incur additional delay in chip operation. Other issues also arise in how to properly control source transistors according to their chip operating modes. Invention and Related Circuits.
FIG. 1A and FIG. 1B illustrate previous source transistor configurations for MTCMOS and a self-reverse biasing scheme, respectively.
FIG. 2 illustrates a timing diagram for the MTCMOS and self-reverse biasing schemes of FIG. 1A-1B. The advantage of the self-reverse biasing scheme over MTCMOS scheme is to suppress leakage current more by forming a self-reverse biased condition between a source transistor (MNS2) and a logic transistor (MPL2). For example, the leakage current can be suppressed by about three orders of magnitude with self-reverse biasing scheme while about one order of magnitude suppression with MTCMOS scheme.
For the MTCMOS scheme shown in active mode in FIG. 1A, the levels of SB1 and S1 as VSS and VDD, respectively, and the level of virtual power (VVDD1) is VDD as shown in FIG. 2. When the chip is in standby mode, SB1 goes to VDD and MPS1 is turned off. The level of WDD1 is lowered by VD1 due to the flow of leakage current MPL1. As the chip goes back to the active mode, SB1 goes to VSS and the lowered virtual power line level (VVDD1) is recovered to VDD when the source transistor is turned on after the level of SB1 goes lower than VDD−VTP (MPS1), where VTP(MPS1) is a threshold voltage of transistor MPS1.
For the self-reverse biasing scheme shown in FIG. 1B, which is similar to the MTCMOS scheme, the voltage level of power line (VVDD2) is lowered by VD2 due to the leakage current flowing through the logic transistor MPL2. The level of the virtual power line is recovered to VDD when the source transistor, MNS2, is turned on. The source transistor is turned on when signal S2 reaches a level of VDD−VD2+VTN(MNS2), where VTN(MNS2) is a threshold voltage of the source transistor, MNS2.
Even though the leakage current can be suppressed more significantly by utilizing the self-reverse biasing scheme, this delays the timing of when a source transistor is turned on to recover the power line level to VDD beyond MTCMOS by an amount represented as tD in FIG. 2. Note that the source transistor in the MTCMOS scheme is turned on at a level of VDD−VTP(MPS1) and at VDD−VDD2+VTN(MNS2) in self-reverse biasing scheme. In consequence to this delay in turning on the source transistor, additional power line recovery time can be required that leads to chip operating delays.
Accordingly a need exists for source transistor configurations and control methods which can achieve fast recovery of virtual power level and proper operations with minimum leakage current. These needs and others are met within the present invention, which overcomes the deficiencies of previously developed circuit configurations and methods.